JTAG/SWD scan pin group
Review the GPIOs that the firmware will test before running a brute-force scan on unknown debug pads.
ESP32-S3 JTAG and SWD pin scanning
Find JTAG and SWD debug pins with ESP32
ESP32 Bit Pirate turns a compatible ESP32-S3 board into a JTAG and SWD pin scanning workbench. Use it to scan candidate debug pins, configure GPIO groups, verify pinouts and move into OpenOCD adapter workflows.
Quick JTAG/SWD workflow
Start with voltage, ground and a limited candidate pin group. Treat scan results as candidates, then verify them with the normal debug workflow before relying on the mapping.
- 01
Confirm target voltage, power state and common ground.
- 02
Wire only the candidate debug pads to selected ESP32 Bit Pirate GPIOs.
- 03
Review or configure the GPIO group used by SWD and JTAG scans.
- 04
Run an SWD scan for ARM-style SWDIO/SWCLK targets, or a JTAG scan for TDI/TDO/TCK/TMS.
- 05
Verify the discovered pinout with OpenOCD or a known debugger setup before deeper target work.
mode jtag
config
scan swd
scan jtag
openocdExample CLI flow. See the JTAG wiki for exact syntax, pin group behavior and firmware-specific options.
JTAG and SWD workflows covered by ESP32 Bit Pirate
Use this overview to choose the right debug workflow before opening a detailed recipe.
SWD pin scanner
Search a controlled candidate set for SWDIO and SWCLK when a board exposes unlabelled ARM debug pads.
JTAG pinout scan
Run a JTAGULATOR-style search for TDI, TDO, TCK and TMS instead of manually trying every wire order.
OpenOCD adapter workflow
Move from discovery to a host-side debug session only after pinout, voltage and target state are confirmed.
Repeatable debug mappings
Save the candidate pinout, voltage and reset notes so later sessions start from a known-safe configuration.
Locked or silent targets
Separate wiring issues from reset, power, security lock or disabled debug interface problems.
When an ESP32-S3 JTAG/SWD workbench helps
Debug headers are not always labelled. A small external scan workflow can reduce blind probing before you connect a full debugger or write an OpenOCD config.
Before guessing pad order
Use a limited candidate GPIO set to explore suspected debug pads without trying every JTAG or SWD combination by hand.
Before OpenOCD
Confirm the basic debug pinout and target voltage before switching to an adapter mode that expects known wiring.
Before blaming the target
Check power, reset state, strap pins and debug locks before assuming a failed scan means the interface is absent.
JTAG/SWD hardware reminders
These notes stay short. The detailed command references live in the project documentation and firmware repository.
ESP32 GPIO uses 3.3 V logic. Confirm the target level before wiring debug pads, and use level adaptation when the target is not safe for direct GPIO connection.
Share ground only after the target power domain is understood. A missing or unsafe ground reference can break scans or damage hardware.
Targets held in reset, deep sleep or low-power modes may not respond even when the JTAG or SWD pins are correct.
Keep the scan group small. JTAG permutation scans get slower and noisier as the number of candidate GPIOs grows.
Common JTAG/SWD problems
Most failures come from voltage, reset, candidate pin choice, target lock state or using adapter mode before discovery is complete.
Check target power, shared ground, candidate pads, reset state and whether SWD is disabled or locked.
Reduce the candidate GPIO group before running permutation scans over TDI, TDO, TCK and TMS.
Repeat the scan with shorter wires, stable target power and a smaller candidate group before documenting the mapping.
Return to pinout, voltage, reset and target configuration checks before changing OpenOCD scripts.
Try SWD first for likely ARM Cortex targets, and JTAG when the board or SoC documentation suggests a full JTAG chain.
Detailed JTAG and SWD recipes
These pages are the task-level workflows. This overview keeps the protocol-level guidance here, while each recipe covers setup, commands and troubleshooting in detail.
Useful JTAG/SWD references
This page is a protocol overview. Use the site index for the full web experience, or GitHub for source code, firmware documentation and the JTAG command reference.
Flash ESP32 Bit Pirate
Flash a supported ESP32-S3 board before testing JTAG mode from the browser.
Open Web FlasherJTAG command reference
Open the maintained firmware wiki for JTAG mode commands and behavior.
Open JTAG command referenceSupported ESP32-S3 boards
Check compatible boards and exposed GPIOs before wiring target debug pads.
Compare supported ESP32-S3 boardsWeb Serial Terminal
Open Web Serial for JTAG commands after the matching firmware is running.
Open Web Serial Terminal for ESP32 Bit PirateUSB adapter modes
Use the dedicated adapter workflow when switching the firmware into OpenOCD or other host-tool modes.
Open USB adapter referenceAll hardware debugging recipes
Browse recipes that connect JTAG work to wiring, commands, captures and troubleshooting.
Browse all hardware debugging recipesESP32 Bit Pirate GitHub
Check firmware source, issues and releases that affect JTAG support.
Open GitHub repositoryJTAG and SWD pin scanning FAQ
Short answers for common questions before moving into a detailed workflow.
Can ESP32 Bit Pirate scan for SWD pins?
Yes. ESP32 Bit Pirate can scan a selected GPIO group to look for SWDIO and SWCLK candidates before verifying the result with a normal debugger workflow.
Can ESP32 Bit Pirate scan a JTAG pinout?
Yes. The JTAG mode can run a JTAGULATOR-style scan over selected candidate pins to look for TDI, TDO, TCK and TMS.
Should I run OpenOCD before scanning pins?
No. Use OpenOCD adapter mode only after target voltage, ground and the debug pinout are known or strongly confirmed.